CY62128EV30 MoBL
®
Switching Waveforms
Figure 6. Read Cycle 1
(Address transition controlled)
t
RC
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Figure 7. Read Cycle No. 2
(OE controlled)
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
CURRENT
t
PU
50%
t
LZCE
DATA VALID
t
PD
50%
t
HZOE
t
HZCE
HIGH
IMPEDANCE
I
CC
I
SB
Figure 8. Write Cycle No. 1
(WE controlled)
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 20
t
HZOE
Notes
15. The device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE
1
transition LOW and CE
2
transition HIGH.
18. Data I/O is high impedance if OE = V
IH
.
19. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
20. During this period, the IOs are in output state. Do not apply input signals.
t
HD
DATA VALID
Document #: 38-05579 Rev. *E
Page 6 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
