PRELIMINARY
Data Byte 12
(continued)
Bit
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
--
--
--
--
--
--
--
Name
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
Pin Description
CY28323
Power On
Default
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be
use to determine the recovery CPU output frequen-
cy.when a Watchdog timer time-out occurs.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When the
FS_Override bit is cleared, the same frequency ratio stat-
ed in the Latched FS[4:0] register will be used. When it is
set, the frequency ratio stated in the SEL[4:0] register will
be used.
Data Byte 13
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Byte 14
Bit
Bit 7
Pin#
--
Name
Pro_Freq_EN
Pin Description
Programmable output frequencies enabled
0 = disabled
1 = enabled
If Prog_Freq_EN is set, the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to
determine the CPU output frequency. The new frequency
will start to load whenever CPU_FSELM[6:0] is updated.
The setting of the FS_Override bit determines the frequen-
cy ratio for CPU and other output clocks. When it is
cleared, the same frequency ratio stated in the Latched
FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Power On
Default
0
Pin#
--
--
--
--
--
--
--
--
Name
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
CPU_FSEL_N0
Pin Description
If Prog_Freq_EN is set, the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to
determine the CPU output frequency. The new frequency
will start to load whenever CPU_FSELM[6:0] is updated.
The setting of the FS_Override bit determines the frequen-
cy ratio for CPU and other output clocks. When it is
cleared, the same frequency ratio stated in the Latched
FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Power On
Default
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Byte 15
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
--
--
--
--
--
--
--
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
0
0
0
0
0
0
0
Pin#
--
--
--
--
--
--
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin Description
Power On
Default
0
0
0
0
0
0
Document #: 38-07004 Rev. *B
Page 11 of 22
CYPRESS [ CYPRESS SEMICONDUCTOR ]
