PRELIMINARY
Data Byte 10
Bit
Bit 7
Bit 6
Bit 5
Pin#
--
--
--
Name
CPU_Skew2
CPU_Skew1
CPU_Skew0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
3V66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Pin Description
CY28323
Power On
Default
0
0
0
Bit 4
Bit 3
Bit 2
--
--
--
Reserved
PCI_Skew1
PCI_Skew0
0
0
0
Bit 1
Bit 0
--
--
3V66_Skew1
3V66_Skew0
0
0
Data Byte 11
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Byte 12
Bit
Bit 7
Pin#
--
Name
ROCV_FREQ_SEL
Pin Description
ROCV_FREQ_SEL determines the source of the recover
frequency when a Watchdog Timer time-out occurs. The
clock generator will automatically switch to the recovery
CPU frequency based on the selection on
ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] &
ROCV_FREQ_M[6:0]
Power On
Default
0
Pin#
--
--
--
--
--
--
--
--
Name
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
Pin Description
If ROCV_FREQ_SEL is set, the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be
use to determine the recovery CPU output frequency
when a Watchdog timer time-out occurs.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When the
FS_Override bit is cleared, the same frequency ratio stat-
ed in the Latched FS[4:0] register will be used. When it is
set, the frequency ratio stated in the SEL[4:0] register will
be used.
Power On
Default
0
0
0
0
0
0
0
0
Document #: 38-07004 Rev. *B
Page 10 of 22
CYPRESS [ CYPRESS SEMICONDUCTOR ]
