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CY2309SC-1HT 参数 Datasheet PDF下载

CY2309SC-1HT图片预览
型号: CY2309SC-1HT
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本3.3 V零延迟缓冲器 [Low Cost 3.3-V Zero Delay Buffer]
分类和应用:
文件页数/大小: 19 页 / 474 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY2305, CY2309
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
Description
Input LOW voltage
Input HIGH voltage
Input LOW current
Input HIGH current
Output LOW voltage
Output HIGH voltage
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (–1)
I
OH
=12 mA (–1H)
I
OH
= –8 mA (–1)
I
OL
= –12 mA (–1H)
REF = 0 MHz
Unloaded outputs at 66.67 MHz, SEL inputs at V
SS
Test Conditions
Min
2.0
2.4
Max
0.8
50.0
100.0
0.4
25.0
35.0
Unit
V
V
μA
μA
V
V
μA
mA
I
DD
(PD mode) Power-down supply
current
I
DD
Supply current
Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices
Parameter
t1
t
DC
t3
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
Name
Output frequency
Duty cycle
= t
2
÷
t
1
Rise time
Fall time
30 pF load
10 pF load
Measured at 1.4 V, F
out
= 66.67 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
Test Conditions
Min
10
10
40.0
1
Typ
50.0
85
5
70
Max
100
133.33
60.0
2.50
2.50
250
±350
8.7
700
200
1.0
Unit
MHz
MHz
%
ns
ns
ps
ps
ns
ps
ps
ms
Output-to-output skew
All outputs equally loaded
Delay, REF rising edge to Measured at V
DD
/2
CLKOUT rising edge
Delay, REF rising edge to Measured at V
DD
/2. Measured in PLL Bypass Mode,
CLKOUT rising edge
CY2309 device only.
Device-to-device skew
Measured at V
DD
/2 on the CLKOUT pins of devices
Cycle-to-cycle jitter
PLL lock time
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on REF
pin
Notes
10. REF input has a threshold voltage of V
DD
/2.
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
12. All parameters specified with loaded outputs
Document Number : 38-07140 Rev. *M
Page 7 of 19