CY2305
CY2309
Pin Description for CY2309
Pin
1
2
3
Signal
Description
Input reference frequency, 5V-tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
REF[1]
CLKA1[2]
CLKA2[2]
VDD
4
5
6
7
8
GND
Ground
CLKB1[2]
CLKB2[2]
S2[3]
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
9
S1[3]
Select input, bit 1
10
11
12
13
14
15
16
CLKB3[2]
CLKB4[2]
GND
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
VDD
3.3V supply
CLKA3[2]
CLKA4[2]
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
CLKOUT[2]
Pin Description for CY2305
Pin
1
2
3
4
5
6
7
Signal
Description
Input reference frequency, 5V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
REF[1]
CLK2[2]
CLK1[2]
GND
CLK3[2]
VDD
CLK4[2]
8
CLKOUT[2]
Select Input Decoding for CY2309
S2
S1
CLOCK A1–A4
Three-state
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
CLKOUT[4]
Driven
Driven
Output Source
PLL
PLL Shutdown
0
0
N
N
Y
N
0
1
PLL
Reference
PLL
1
0
Driven
Driven
1
1
Driven
Driven
Driven
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07140 Rev. *G
Page 2 of 14
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