CY2305
CY2309
Pin Description for CY2309
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
CLKA1
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
GND
V
DD
CLKA3
[2]
CLKA4
[2]
CLKOUT
[2]
[2]
[2]
Signal
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Description
Input reference frequency, 5V-tolerant input
CLKA2
[2]
CLKB4
[2]
Buffered output, internal feedback on this pin
Pin Description for CY2305
Pin
1
2
3
4
5
6
7
8
REF
[1]
CLK2
[2]
CLK1
[2]
GND
CLK3
[2]
V
DD
CLK4
[2]
CLKOUT
[2]
Signal
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Description
Input reference frequency, 5V-tolerant input
Select Input Decoding for CY2309
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
[4]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07140 Rev. *G
Page 2 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
