CY2305
CY2309
Typical Duty Cycle
[8]
and I
DD
Trends
[9]
for CY2305-1 and CY2309-1
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
60
58
56
Duty Cycle (% )
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
58
56
Duty Cycle (% )
54
52
50
48
46
44
42
40
33 MHz
66 MHz
100 MHz
133 MHz
54
52
50
48
46
44
42
40
3
3.1
3.2
3.3
VDD (V)
3.4
3.5
3.6
33 MHz
66 MHz
100 MHz
3
3.1
3.2
3.3
VDD (V)
3.4
3.5
3.6
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
60
58
56
Duty Cycle (%)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
60
58
56
Duty Cycle (%)
-40C
0C
25C
70C
85C
54
52
50
48
46
44
42
40
20
40
60
80
Frequency (MHz)
100
120
140
54
52
50
48
46
44
42
40
20
40
60
80
Frequency (MHz)
100
120
140
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
140
120
100
IDD (mA)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
120
100
IDD (mA)
33 MHz
66 MHz
100 MHz
80
60
40
20
0
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
80
60
40
20
0
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
33 MHz
66 MHz
100 MHz
Notes:
8. Duty Cycle is taken from typical chip measured at 1.4V.
9. I
DD
data is calculated from I
DD
= I
CORE
+ nCVf, where I
CORE
is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply
Voltage (V); f = frequency (Hz)).
Document #: 38-07140 Rev. *G
Page 8 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
