CY2304
Pin Description
Pin
1
2
3
4
5
6
7
8
REF
[1]
CLKA1
CLKA2
GND
CLKB1
[2]
CLKB2
[2]
V
DD
FBK
[2]
[2]
Signal
Clock output, Bank A
Clock output, Bank A
Ground
Clock output, Bank B
Clock output, Bank B
3.3V supply
PLL feedback input
Description
Input reference frequency, 5V-tolerant input
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2304, the FBK pin can be
driven from any of the four available output pins. The output
driving the FBK pin will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the
input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2304, refer to the appli-
cation note “CY2308:
Zero Delay Buffer.”
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
Document #: 38-07247 Rev. *C
Page 2 of 8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
