CY2292
Switching Characteristics, Industrial 5.0V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range, 5V
CY2292I
11.1
13000
ns
operation
(90 MHz)
(76.923 kHz)
CY2292FI
12.5
13000
ns
(80 MHz)
(76.923 kHz)
[12]
[12]
Output Duty
Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1
40%
50%
50%
60%
fOUT > 66 MHz
Duty cycle for outputs, defined as t2 ÷ t1
45%
55%
fOUT < 66 MHz
t3
t4
t5
Rise Time
Fall Time
Output clock rise time[13]
3
2.5
10
5
4
15
ns
ns
ns
Output clock fall time[13]
Output Disable
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time
t6
t7
t8
Output Enable
Time
Skew
Time for output to leave three-state mode after
10
15
0.5
20.0
1
ns
ns
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs[3, 12, 14]
Frequency transition rate
< 0.25
CPUCLK Slew
Clock Jitter[14]
Clock Jitter[14]
1.0
MHz/
ms
%
t9A
t9B
Peak-to-peak period jitter (t9A max. – t9A min.), %
of clock period (fOUT < 4 MHz)
< 0.5
< 0.7
Peak-to-peak period jitter (t9B max. – t9B min.) (4
1
ns
MHz < fOUT < 16 MHz)
t9C
t9D
t10A
t10B
Clock Jitter[14]
Clock Jitter[14]
Lock Time for CPLL Lock Time from Power-up
Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz)
Peak-to-peak period jitter (fOUT > 50 MHz)
< 400
< 250
<25
500
350
50
ps
ps
ms
ms
Lock Time for
Lock Time from Power-up
<0.25
1
UPLL and SPLL
Slew Limits
CPU PLL Slew Limits
CY2292I
CY2292FI
20
20
90
80
MHz
MHz
Switching Characteristics, Industrial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range, 3.3V CY2292I
15
13000
ns
operation
(66.6 MHz)
(76.923 kHz)
CY2292FI
16.66
13000
ns
(60 MHz)
(76.923 kHz)
[12]
[12]
Output Duty
Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1
40%
45%
50%
50%
60%
55%
fOUT > 66 MHz
Duty cycle for outputs, defined as t2 ÷ t1
fOUT < 66 MHz
t3
t4
t5
Rise Time
Fall Time
Output clock rise time[13]
3
2.5
10
5
4
15
ns
ns
ns
Output clock fall time[13]
Output Disable
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time
t6
t7
t8
Output Enable
Time
Skew
Time for output to leave three-state mode after
10
15
0.5
ns
ns
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs[3, 12, 14]
Frequency transition rate
< 0.25
CPUCLK Slew
1.0
20.0
MHz/ms
Document #: 38-07449 Rev. *B
Page 7 of 11
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