CY2292
Switching Characteristics, Industrial 3.3V (continued)
Parameter
t9A
Name
Description
Min.
Typ.
< 0.5
Max.
1
Unit
%
Clock Jitter[14]
Peak-to-peak period jitter (t9A max. – t9A min.),
% of clock period (fOUT < 4 MHz)
t9B
Clock Jitter[14]
Clock Jitter[14]
Clock Jitter[14]
Peak-to-peak period jitter (t9B max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
< 0.7
< 400
< 250
< 25
1
500
350
50
ns
ps
t9C
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
t9D
Peak-to-peak period jitter
(fOUT > 50 MHz)
Lock Time from Power-up
ps
t10A
t10B
Lock Time for
CPLL
ms
ms
Lock Time for
Lock Time from Power-up
< 0.25
1
UPLL and SPLL
Slew Limits
CPU PLL Slew Limits
CY2292I
CY2292FI
20
20
66.6
60
MHz
MHz
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t
1
t
2
OUTPUT
t
3
t
4
[4]
Output Three-State Timing
OE
t
5
t
6
ALL
THREE-STATE
OUTPUTS
CLK Outputs Jitter and Skew
t
9A
CLK
OUTPUT
t7
RELATED
CLK
CPU Frequency Change
OLD SELECT
NEW SELECT STABLE
t & t F
new
SELECT
F
old
8
10
CPU
Document #: 38-07449 Rev. *B
Page 8 of 11
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