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CY2292FXC 参数 Datasheet PDF下载

CY2292FXC图片预览
型号: CY2292FXC
PDF下载: 下载PDF文件 查看货源
内容描述: 三锁相环通用的EPROM可编程时钟发生器 [Three-PLL General-Purpose EPROM Programmable Clock Generator]
分类和应用: 时钟发生器可编程只读存储器电动程控只读存储器
文件页数/大小: 11 页 / 190 K
品牌: CYPRESS [ CYPRESS ]
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CY2292  
Switching Characteristics, Commercial 5.0V (continued)  
Parameter  
t9A  
Name  
Description  
Min.  
Typ.  
<0.5  
Max.  
1
Unit  
%
Clock Jitter[14]  
Peak-to-peak period jitter (t9A max. – t9A  
min.), % of clock period (fOUT < 4 MHz)  
t9B  
Clock Jitter[14]  
Peak-to-peak period jitter (t9B max. – t9B  
min.)  
<0.7  
1
ns  
ps  
(4 MHz < fOUT < 16 MHz)  
t9C  
Clock Jitter[14]  
Peak-to-peak period jitter (16 MHz < fOUT  
<
<400  
500  
50 MHz)  
t9D  
t10A  
t10B  
Clock Jitter[14]  
Lock Time for CPLL  
Lock Time for UPLL and Lock Time from Power-up  
Peak-to-peak period jitter (fOUT > 50 MHz)  
Lock Time from Power-up  
<250  
<25  
<0.25  
350  
50  
1
ps  
ms  
ms  
SPLL  
Slew Limits  
CPU PLL Slew Limits  
CY2292  
CY2292F  
20  
20  
100  
90  
MHz  
MHz  
Switching Characteristics, Commercial 3.3V  
Parameter  
Name  
Description  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Period  
Clock output range, 3.3V CY2292  
12.5  
13000  
ns  
operation  
(80 MHz)  
(76.923 kHz)  
CY2292F  
15  
13000  
ns  
(66.6 MHz)  
(76.923 kHz)  
[12]  
[12]  
Output Duty  
Cycle[11]  
Duty cycle for outputs, defined as t2 ÷ t1  
40%  
50%  
50%  
60%  
fOUT > 66 MHz  
Duty cycle for outputs, defined as t2 ÷ t1  
45%  
55%  
fOUT < 66 MHz  
t3  
t4  
t5  
Rise Time  
Fall Time  
Output clock rise time[13]  
Output clock fall time[13]  
3
2.5  
10  
5
4
15  
ns  
ns  
ns  
Output Disable  
Time for output to enter three-state mode after  
Time  
SHUTDOWN/OE goes LOW  
t6  
t7  
t8  
Output Enable  
Time  
Skew  
Time for output to leave three-state mode after  
SHUTDOWN/OE goes HIGH  
10  
15  
0.5  
20.0  
1
ns  
ns  
Skew delay between any identical or related  
< 0.25  
outputs[3, 12, 14]  
CPUCLK Slew  
Clock Jitter[14]  
Clock Jitter[14]  
Frequency transition rate  
1.0  
MHz/  
ms  
%
t9A  
t9B  
Peak-to-peak period jitter (t9A max. – t9A min.),  
% of clock period (fOUT < 4 MHz)  
< 0.5  
< 0.7  
Peak-to-peak period jitter (t9B max. – t9B min.)  
1
ns  
(4 MHz < fOUT < 16 MHz)  
t9C  
t9D  
t10A  
t10B  
Clock Jitter[14]  
Clock Jitter[14]  
Lock Timefor CPLL Lock Time from Power-up  
Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz)  
Peak-to-peak period jitter (fOUT > 50 MHz)  
< 400  
< 250  
< 25  
500  
350  
50  
ps  
ps  
ms  
ms  
Lock Time for  
Lock Time from Power-up  
< 0.25  
1
UPLL and SPLL  
Slew Limits  
CPU PLL Slew Limits  
CY2292  
CY2292F  
20  
20  
80  
66.6  
MHz  
MHz  
Document #: 38-07449 Rev. *B  
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