CY22381
CY223811
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ..............................................–0.5 V to +7.0 V
DC input voltage .............................–0.5 V to + (V
DD
+ 0.5 V)
Storage temperature..................................... –65 °C +125 °C
Junction temperature.................................................. 125 °C
Data retention at Tj = 125 °C.................................> 10 years
Maximumrprogamming cycles..........................................100
Package power dissipation....................................... 250 mW
Static discharge voltage
(per MIL-STD-883, Method 3015) ...........................
2000V
Latch up (per JEDEC 17) ....................................
±200 mA
Operating Conditions
Parameter
V
DD
T
A
Supply voltage
Commercial operating temperature, ambient
Industrial operating temperature, ambient
C
LOAD_OUT
Max. load capacitance
f
REF
External reference crystal
External reference clock
, cCommercial
External reference clock
, industrial
t
PU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
Description
Min
3.135
0
–40
–
8
1
1
0.05
Typ
3.3
–
–
–
–
–
–
–
Max
3.465
+70
+85
15
30
166
150
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
ms
Recommended Crystal Specifications
Parameter
F
NOM
C
LNOM
R
1
DL
Description
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance Fundamental mode
(ESR)
Crystal drive level
No external series resistor assumed
Description
Parallel resonance, fundamental mode
Min
8
8
–
–
Typ.
–
–
–
0.5
Max
30
20
50
2
Unit
MHz
pF
mW
Electrical Characteristics
Parameter
I
OH
I
OL
C
XTAL_MIN
C
XTAL_MAX
C
IN
V
IH
V
IL
I
IH
I
IL
I
OZ
Description
Output high current
Output low current
Crystal load capacitance
Crystal load capacitance
Input pin capacitance
HIGH-level input voltage
LOW-level input voltage
Input HIGH current
Input LOW current
Output leakage current
Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5 V, V
DD
= 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of V
DD
CMOS levels,% of V
DD
V
IN
= V
DD
– 0.3 V
V
IN
= +0.3 V
Three-state outputs
Min
12
12
–
–
–
70%
–
–
–
–
Typ
24
24
6
30
7
–
–
<1
<1
–
Max
–
–
–
–
–
–
30%
10
10
10
Unit
mA
mA
pF
pF
pF
V
DD
V
DD
A
A
A
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
3. Guaranteed by design, not 100% tested.
Document #: 38-07012 Rev. *I
Page 5 of 11
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