CG64xxAM Preliminary Data Sheet
PSoC™ Overview
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is highlighted below.
Array Input
Configuration
PSoC Device Characteristics
ACI0[1:0]
ACI1[1:0]
PSoC Device
Group
ACOL1MUX
CY8C29x66
CY8C27x43
CY8C24794
CY8C24x23A
CY8C24x23
CY8C21x34
64
44
56
24
24
28
4
2
1
1
1
1
16
8
12
12
48
12
12
28
4
4
2
2
2
0
4
4
2
2
2
2
12
12
6
2K
32K
16K
16K
4K
Array
256 Bytes
1K
4
ACE00
ASE10
ACE01
ASE11
4
6
256 Bytes
256 Bytes
512 Bytes
4
6
4K
4a
4
8K
4a
CY8C21x23
16
1
4
8
0
2
256 Bytes
4K
a. Limited analog functionality.
Analog System Block Diagram
Example Application
Additional System Resources
To develop an application for CG6462, use the CY8C21123 in
the development tools. To develop an application for CG6457,
use the CY8C21323 in the development tools. Following is a
high-level diagram of an ideal application using this device.
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a switch mode pump, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
Analog
or
Digital
Hall
Sensor
1 or 2
Phase
Coil
Dutycycle
orAnalog
Speed
Tachometer
or Locked
RotorOutput
Hardware
Current
Limit
Up to 2
Thermistors
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
FETs
Input
GPIO
PSoC
CORE
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
SystemBus
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
Global Digital Interconnect
Global Analog Interconnect
Internal
SROM
Flash
SRAM
Oscillator
CPUCore
Sleep and
Watchdog
Interrupt
Controller
(M8C)
■ An internal 1.3 voltage reference provides an absolute refer-
ence for the analog system, including ADCs and DACs.
PIDClosedLoopSpeed
Software Current Limit
Control
DIGITAL SYSTEM
ANALOG SYST EM
OutputPWM
ThermistorandInput
ADC
TachometerTimer
AnalogHall
or
Hardware Current
Limit
InputDutycycle
Timers
Comparator
I2C
Fan Controller Block Diagram
May 24, 2005
Document No. 001-00353 Rev. **
3
CYPRESS [ CYPRESS ]
