CG64xxAM Preliminary Data Sheet
PSoC™ Overview
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is highlighted below.
PSoC Device Characteristics
Amount of SRAM
Analog Columns
Digital IO
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
PSoC Device
Group
ACOL1MUX
CY8C29x66
64
44
56
24
24
28
16
4
2
1
1
1
1
1
16
8
4
4
4
4
4
12
12
48
12
12
28
8
4
4
2
2
2
0
0
4
4
2
2
2
2
2
12
12
6
6
6
4
a
4
a
2K
256 Bytes
1K
256 Bytes
256 Bytes
512 Bytes
256 Bytes
32K
16K
16K
4K
4K
8K
4K
Array
CY8C27x43
CY8C24794
ACE00
ASE10
ACE01
ASE11
CY8C24x23A
CY8C24x23
CY8C21x34
CY8C21x23
Analog System Block Diagram
a. Limited analog functionality.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a switch mode pump, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
■
Example Application
To develop an application for CG6462, use the CY8C21123 in
the development tools. To develop an application for CG6457,
use the CY8C21323 in the development tools. Following is a
high-level diagram of an ideal application using this device.
Analog
or
Digital
Hall
Sensor
1 or 2
Phase
Coil
FETs
Dutycycle
or Analog
Speed
Input
T achometer
or Locked
RotorOutput
Up to 2
Thermistors
Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 voltage reference provides an absolute refer-
ence for the analog system, including ADCs and DACs.
Hardware
Current
Limit
GPIO
■
PSoC
CORE
SystemBus
■
Global Digital Interconnect
Global Analog Interconnect
SRAM
Interrupt
Controller
PID ClosedLoop Speed
Control
Internal
Oscillator
SROM
Flash
CPU Core
(M8C)
Sleep and
Watchdog
■
Software Current Limit
DIGITAL SYSTEM
OutputPWM
TachometerT imer
Input Dutycycle
T imers
I2C
ANALOG SYSTEM
T hermistorand Input
ADC
Analog Hall
or
Hardware Current
Limit
Comparator
Fan Controller Block Diagram
May 24, 2005
Document No. 001-00353 Rev. **
Amount of Flash
Analog Outputs
Analog Blocks
Analog Inputs
Digital Blocks
Digital Rows
3
CYPRESS [ CYPRESS SEMICONDUCTOR ]
