CG64xxAM Preliminary Data Sheet
PSoC™ Overview
CPU core, called the M8C, is a powerful processor with speeds
up to 12 MHz. The M8C is a two MIPS 8-bit Harvard architec-
ture microprocessor.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal
arrays, I2C functionality for implementing an I2C master, slave,
multi-master, an internal voltage reference that provides an
absolute value of 1.3V to a number of PSoC subsystems, and
various system resets supported by the M8C.
The Digital System is composed of an array of digital PSoC
blocks, which can be configured into any number of digital
peripherals. The digital blocks can be connected to the GPIO
through a series of global busses that can route any signal to
any pin. Freeing designs from the constraints of a fixed periph-
eral controller.
The Analog System is composed of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
8 bits in precision.
DigitalClocks
FromCore
Port 1
Port 0
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
8
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral configura-
tions include those listed below.
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Digital System Block Diagram
The Analog System
The Analog System is composed of 4 configurable blocks to
allow creation of complex analog signal flows. Analog peripher-
als are very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are listed
below.
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PWMs (8 to 32 bit)
PWMs with Dead band (8 to 24 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity
SPI master and slave
I2C slave, master, multi-master (1 available as a System
Resource)
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to 4)
Pseudo Random Sequence Generators (8 to 32 bit)
Analog-to-digital converters (single or dual, with 10-bit reso-
lution)
Pin-to-pin comparators (1)
Single-ended comparators (up to 2) with absolute (1.3V) ref-
erence
1.3V reference (as a System Resource)
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The digital blocks can be connected to any GPIO through a
series of global busses that can route any signal to any pin. The
busses also allow for signal multiplexing and for performing
logic operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled
“PSoC Device Charac-
teristics” on page 3.
In most PSoC devices, analog blocks are provided in columns
of three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CG64xxAM devices provide
limited functionality Type “E” analog blocks. Each column con-
tains one CT block and one SC block.
The number of blocks is on the device family which is detailed
in the table titled
“PSoC Device Characteristics” on page 3.
May 24, 2005
Document No. 001-00353 Rev. **
2
CYPRESS [ CYPRESS SEMICONDUCTOR ]
