CG6233AS
MPEG Clock Generator with VCXO
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
• Lower drive strength settings
Benefits
• Highest-performance PLL tailored for multimedia applica-
tions
• Meets critical timing requirements in complex system
designs
• Application compatibility for a wide variety of designs
• Electromagnetic interference (EMI) reduction for standards
compliance
Frequency Table
Part
Number
CG6233AS
Outputs
1
Input Frequency Range
Output
Frequencies
VCXO Control
Curve
Other Features
Pinout compatible with MK3727
13.5-MHz pullable crystal input One copy of 27 MHz linear
per Cypress specification
Block Diagram
13.5 XIN
XOUT
OSC
PLL
OUTPUT
DIVIDER
27 MHz
VCXO
VDD
VSS
Pin Configuration
CG6233AS
8-pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
NC or VSS
NC or VDD
27 MHz
Cypress Semiconductor Corporation
Document #: 38-07625 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 15, 2004
CYPRESS [ CYPRESS SEMICONDUCTOR ]
