+/+
Preliminary
Product Features
•
•
•
•
•
…when timing is critical
C9853
High Performance Pentium
®
III Clock Generator
Two differential host clocks pairs
One 3V Mref reference clock for memory reference
seeds (separate single ended, but 180 degrees out
of phase)
Three 3V, 66 MHz clocks
Ten 3V, 33 MHz PCI clocks
Two 48 MHz clocks
•
•
•
•
Two 14.318 MHz reference clocks
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
External resistor for current reference
48 Pin SSOP and TSSOP Package
Frequency Selection Table
SEL 133/100
0
0
0
0
1
1
1
1
SELA
0
0
1
1
0
0
1
1
SELB
0
1
0
1
0
1
0
1
CPU(1:2)/
CPU# (1:2)
100 MHz
105 MHz
200 MHz
Hi-Z
133 MHz
126.7 MHz
200 MHz
XIN/2
3Vmref/
3Vmref_b
50 MHz
52.5MHz
50 MHz
Hi-Z
66.7 MHz
63.3 MHz
66.7 MHz
XIN/4
3V66 (0:2)
66.7 MHz
70.0 MHz
66.7 MHz
Hi-Z
66.7 MHz
63.3 MHz
66.7 MHz
XIN/4
PCI (1:10)
33.3 MHz
35.0 MHz
33.3 MHz
Hi-Z
33.3 MHz
31.7 MHz
33.3 MHz
XIN/8
48M
(0:1)
48 MHz
48 MHz
48 MHz
Hi-Z
48 MHz
48 MHz
48 MHz
XIN/2
Ref (1:2)
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
XIN
Block Diagram
VDDR
Ref1/MultSel0
Ref2/MultSel1
Sel2
VSSR
3VMRef
3VMRef_b
SEL#
SEL100/133
SPREAD#
PWRDWN#
Pin Configuration
Ref2/MultSel1
VDDR
XIN
XOUT
VSSP
PCI1
PC2
VDDP
PCI3
PCI4
VSSP
PCI5
PCI6
VDDP
PCI7
PCI8
VSSP
PCI9
PCI10
VDDP
Sel100/133
VSSU
48M0/SelA
48M1/SelB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Ref1/MultSel0
VSSR
VDDM
3VMref
3VMref_b
VSSM
Spread#
CPU1
CPU1#
VDDC
CPU2
CPU2#
VSSC
I_Ref
VDD
VSS
PwrDwn#
VDDL
3V66_0
3V66_1
VSSL
3V66_2
VDDL
VDDU
Sel1
XIN
XOUT
OSC
VCO1
I_REF
VDDC
CPU(1:2)
CPU#(1:2)
VSSC
VDDL
3V66(0:2)
VSSL
VDDP
PCI (1:10)
VSSP
VCO2
SELA/B
2
VDDU
48M(0:1)
VSSU
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA TEL 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
1.0
4/13/2000
Page 1 of 16
CYPRESS [ CYPRESS SEMICONDUCTOR ]
