C9843
Clock Generator for Pentium Systems with SDRAM Support
Preliminary
Byte 6: Dial –A- Frequency™ Control Register (1 = Enable, 0 =
Byte 7: Silicon Signature Register (1 = Enable, 0 = Disable)
Disable)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Year Code
00=year 2000
Product Revision code
000 = Rev A
Bit
7
@Pup
Pin#
Description
Reserved
R5 (MSB)
R4
R3
R2
R1
R0 (LSB)
0
0
0
0
0
0
1
1
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
6
5
4
3
2
1
0
Vendor Code
011 = IMI
N and R register enabled
Note: The Pin# column lists the relevant pin number
where applicable. The @Pup column gives the default
state at power up. Byte 7 is a read only register
Clock Waveforms for Single-Ended Clock Outputs
Output
Buffer
Test Point
Test Load
Clock Output Wave
Tperiod
Tperiod
Duty Cycle
Thigh
Duty Cycle
Thigh
2.5V
Clocking
Interface
3.3V
Clocking
Interface
2.0
2.5
0.4
2.4
2.5
0.4
Tlow
Tlow
Trise
Tfall
Trise
Tfall
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035, USA TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev 1.0
3/30/2000
Page 10 of 13
CYPRESS [ CYPRESS ]
