C9835
Table 4. Group Timing Relationships and Tolerances
(continued)
CPU = 66.6 MHz, SDRAM = 100 MHz
CPU = 133.3MHz, SDRAM = 133.3MHz
Offset(ns)
CPU to SDRAM/DCLK
CPU to 3V66
SDRAM/DCLK to 3V66
3V66 to PCI
PCI to IOAPIC
48M (0,1)
3.75
0
3.75
1.5–3.5
0
Async
Tolerance(ps)
500
500
500
500
1000
N/A
is high indicates the end of a data transfer cycle. Data is
always sent as complete 8-bit bytes, after which an
acknowledge is generated. The first byte of a transfer cycle is
an 8-bit address. The LSB address Byte = 0 in write mode.
The device will respond to transfers of 10 bytes (max) of data.
The device will generate an acknowledge (low) signal on
SDATA following reception of each byte. Data is transferred
MSB first at a max rate of 100kbits/s. This device will also
respond to a D3 address which sets it in a read mode. It will
not respond to any other control interface conditions, and
previously set control registers are retained.
When a clock driver is placed in power down mode, the
SMBUS signals SDATA and SCLK must be tri-stated. In power
down, the device retains all SMBUS programming information.
ACK
BYTE COUNT
(Don’t Care)
ACK
BYTE 0
(Valid)
ACK
BYTE N
(Valid)
ACK
Conditions
180 degrees phase shift
3V66 leads
2-Wire SMBUS Control Interface
The 2-wire control interface implements a read/write slave
only interface according to SMBus specification. (SeeFigure
5
below). The device can be read back by using standard
SMBUS command bytes. Sub addressing is not supported,
thus all preceding bytes must be sent in order to change one
of the control bytes. The 2-wire control interface allows each
clock output to be individually enabled or disabled. 100 Kbits/s
(standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes
when the SCLK signal is low, and is stable when SCLK is high.
There are two exceptions to this. A high to low transition on
SDATA while SCLK is high is used to indicate the start of a data
transfer cycle. A low to high transition on SDATA while SCLK
Transmit
Receive
DATA
MSB
LSB
ACK
1
1
0
1
0
0
1
0
COMMAND BYTE
(Don’t Care)
CLK
START CONDITION
8
8
8
8
STOP CONDITION
Figure 5a (WRITE Cycle)
Transmit
ACK BYTE COUNT
ACK
(Valid)
(Valid)
BYTE 0
ACK
(Valid)
BYTE1
ACK
BYTE N
ACK
(Valid)
Receiv
DATA
1
1
0
1
0
0
1
1
MSB
LSB
CLK
START CONDITION
8
8
8
8
STOP CONDITION
Figure 5b (READ Cycle)
Figure 5. SMBus Communications Waveforms
Document #: 38-07303 Rev. **
Page 7 of 18
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