C9835
Maximum Ratings
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:....................................0°C to +85°C
Maximum ESD Protection.............................................. 2 KV
Maximum Power Supply: ................................................5.5V
This device contains circuitry that protects the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD = VDDS = 3.3V ± 5%, VDDC = VDDI = 2.5V ± 5%, TA = 0°C to +70°C[20]
Parameter
VIL1
Description
Input Low Voltage
Conditions
Min.
Typ.
Max.
Units
V
Note 21
1.0
VIH1
Input High Voltage
2.0
V
VIL2
Input Low Voltage
Note 22
1.0
V
VIH2
Input High Voltage
2.2
V
IIL1
Input Low Current (@VIL = VSS
)
For internal pull-up resistors[23]
–20
20
10
295
60
75
90
1
µA
µA
µA
mA
mA
mA
mA
mA
mA
pF
pF
nH
pF
V
IIH1
Input High Current (@VIH =VDD
Three-state leakage Current
Dynamic Supply Current
)
Ioz
Idd3.3V
Idd2.5V
CPU @ 66 MHz
CPU @ 100 MHz
CPU @ 133 MHz
PD# = “0”
Dynamic Supply Current
Ipd3.3V
Ipd2.5V
Cin
Power Down Supply Current
Power Down Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
PD# = “0”
1
5
Cout
6
Lpin
7
Cxtal
VBIAS
Txs
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Measured from Pin to Ground[24]
From stable 3.3V power supply.
34
36
38
0.7VDD
40
0.3VDD
VDD/2
µs
Table 7. Maximum Output Load
Clock Name
Max Load (in pF)
CPU(0:2), IOAPIC(0:1), REF, 48M0 (USB), VCH_CLK
PCI(0:6), SDRAM(0:5), DCLK, 3V66(0:2)
48M1 (DOT)
20
30
15
Notes:
20. All outputs loaded per Table 7.
21. Applicable to input signals : SEL(0:1), PD# (pull-up).
22. Applicable to SDATA and SCLK.
23. Internal pull-up and pull-down resistors affect this current.
24. See Applications data that is presented later in this datasheet on crystal interfacing.
Document #: 38-07303 Rev. **
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