+/+
Approved Product
Product Features
•
•
•
•
•
•
•
•
•
•
•
•
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…when timing is critical
C9829B
Low EMI Clock Generator for Intel
®
133MHz/3DIMM Chipset Systems
Frequency Table (MHz)
SEL
(3:0)**
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPU
66.67
100.00
133.33
133.33
83.35
106.91
150.00
120.96
89.90
125.02
200.00
116.87
100.00
112.00
166.53
140.00
PCI
SDRAM 3V66 /IOAPIC
REF
DOT USB
100.00* 66.67
33.33 14.318M 48M 48M
100.00* 66.67
33.33 14.318M 48M 48M
133.33 66.67
33.33 14.318M 48M 48M
100.00* 66.67
33.33 14.318M 48M 48M
125.02 83.35
41.67 14.318M 48M 48M
106.91 71.27
35.64 14.318M 48M 48M
150.00 75.00
37.50 14.318M 48M 48M
120.96 80.64
40.32 14.318M 48M 48M
134.86 89.90
44.95 14.318M 48M 48M
125.02 83.35
41.67 14.318M 48M 48M
200.00 100.00 50.00 14.318M 48M 48M
116.87 77.91
38.96 14.318M 48M 48M
133.33 66.67
33.33 14.318M 48M 48M
112.00 74.67
37.33 14.318M 48M 48M
166.53 83.27
41.63 14.318M 48M 48M
105.00 70.00
35.00 14.318M 48M 48M
Designed for Intel’s 133MHz/SDRAM chipset
2 copies of CPU Clock (CPU[0:1])
13 copies of SDRAM Clock (SDRAM[0:12])
7 copies of PCI Clocks
3 copies of 3V66 Clock
1 IOAPIC Clock, synchronous to PCI Clock
1 REF Clock
1 USB Clock (Non SSC)
1 DOT Clock (Non SSC)
IMI Spread Spectrum for best EMI reduction
Dial-a-Frequency™ Feature
Dial-a-dB™ Feature
56 Pin SSOP
Block Diagram
XIN
36pF
300K
36pF
XOUT
1
VDD
REF / Sel1
Table1
*Will be set to 133 MHz, I C Byte3, Bit0 is set to a Logic 1.
**Sel0 also controls TS# functionality if TS# is 0 at power up.
2
Pin Configuration
IOAPIC
VDDI
VSS
REF / Sel1
VDD
Xin
Xout
VSS
VDD
3V66-0
3V66-1
3V66-2
VSS
PCI0 / Sel3
PCI1
PCI2
VDD
VSS
PCI3
PCI4
PCI5
PCI6
Sel0
VSS
VDD
SCLK
SDATA
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSS
VDDC
CPU0
CPU1
VSS
SDRAM0
SDRAM1
VDDS
VSS
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDS
VSS
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDDS
VSS
SDRAM10
SDRAM11
SDRAM12
TS# / PD#
DOT
USB / Sel2
VDD
VDDI
S1
apic
1
VDDC
cpu
Rin
SCLK
SDATA
SEL0
TS#/PD#
s2
s3
PLL1
i2c-clk
i2c-data
s0
pwr_dwn#
pci
4
1
sdram
13
VDD
3V66
3
VDD
PCI(1:6)
PCI0/Sel3
3V66(0:2)
2
VDDS
SDRAM(0:12)
CPU(0:1)
IOAPIC
VDD
Rin
PD#
1
i2c-clk
i2c-data
PLL2
USB/Sel2
48
1
VDD
DOT
Fig.1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
4/12/2000
Page 1 of 20
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