Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
VTT_PWRGD# Timing Diagram
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Delay
Clock State
State 0
Off
State 1
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Off
Note A: Device is not effected, VTT_PWRGD# is ignored.
Clock Generator PowerUp/Run State Diagram
S1
S2
Sample
Inputs (pins
54,55)
Delay 0.25mS
Enable Outputs
VDDA = 2.0V
S0
S3
Normal
Operation
Power Off
VDD3.3 = Off
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 21 of 25
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