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C9827H 参数 Datasheet PDF下载

C9827H图片预览
型号: C9827H
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能的Pentium 4的时钟合成器 [High Performance Pentium 4 Clock Synthesizer]
分类和应用: 时钟
文件页数/大小: 25 页 / 172 K
品牌: CYPRESS [ CYPRESS ]
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Approved Product  
C9827H  
High Performance Pentium® 4 Clock Synthesizer  
CPU_STP# - Assertion (transition from logic ‘1’ to logic ‘0’)  
When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via  
assertion of CPU_STP# will be stopped after being sampled by 2 falling CPU clock edges. The final state of the  
stopped CPU signals is CPU = high and CPU0# = Low. There is no change to the output drive current values during  
the stopped state. The CPU is driven high with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPU# signal  
will not be driven. Due to external pulldown circuitry CPU# will be low during this stopped state.  
CPU_STP#  
CPU  
CPU#  
Assertion CPU_STP# Waveform Figure  
CPU_STP# Functionality Table  
CPU_STP#  
CPU#4  
Normal  
Iref*Mult  
CPU  
Normal  
Float  
DRCG  
66M  
66M  
66CLK(0:2)  
66Input  
66Input  
PCI_F/PCI  
66Input/2  
66Input/2  
PCI  
66Input/2  
66Input/2  
USB/DOT  
48M  
1
0
48M  
CPU_STP# De-assertion (transition from logic ‘0’ to logic ‘1’)  
The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation  
in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces  
when the clock resumes. The maximum latency from the de-assertion to active outputs is no more than 2 CPU clock  
cycles.  
Cypress Semiconductor Corporation  
http://www.cypress.com  
Document#: 38-07106 Rev. *A  
12/26/2002  
Page 16 of 25  
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