C9820
Direct Rambus Clock Generator
Preliminary
Device Characteristics
Characteristic
Symbol
DC
Min
Typ
50%
-
Max
60%
Units
t cycle
nS
Conditions
Output Duty Cycle over 10,000 cycles
Clock cycle time
Jitter over 1-6 clock cycles at 400 Mhza
Jitter over 1-6 clock cycles at 300 Mhza
Jitter over 1-6 clock cycles at 267 MHza
Phase Aligner phase step size (at Clk/ClkB)
40%
tCYCLE
2.5
3.75
100
140
160
-
pS
tj
-
-
pS
pS
tSTEP
2
pS
Phase Detector phase error for distributed loop
Measured at PcklM-SynclkN (rising edges) (does not
include clock Jitter)
tERR,PD
-100
-
100
pS
PLL output phase error when tracking SSC
Output voltage during Clk Stop (StopB=0)
Output crossing-point voltage
tERR,SSC
VX,STOP
VX
-100
1.1
1.3
0.4
-
-
-
-
-
-
-
-
-
100
2.0
1.8
0.6
2.0
-
pS
V
V
Output voltage swingb
VCOS
VOH
V
Output high voltage
V
Output low voltage
VOL
1.0
12
-
V
Output dynamic resistance (at pins)c
Output current during Hi-Z (S0=1, S1=1)
Output current during Clk Stop (StopB=0)
Cycle-to-cycle duty cycle error at 400 MHz
Cycle-to-cycle duty cycle error at 300 MHz
Cycle-to-cycle duty cycle error at 267 MHz
ROUT
IOZ
50
Ω
50
µA
µA
pS
pS
pS
pS
IOZ,STOP
-
500
50
-
-
-
-
-
tDC,ERR
-
70
-
80
Output rise and fall times (measured at 20% - 80% of
output voltage)
tCR, tCF
tCR, tCF
250
500
Difference between rise and fall times on the same
pin of a single device (20% - 80%)
-
100
pS
=3.3V ± 5%, TA = 0ºC to +70ºC
a. Output short term jitter spec is peak to peak.
b. VCOS = VOH – VOL
c. ROUT= ∆VO/∆IO. This is defined at the output pins, not at the measurement point.
Table 11: Device Characteristics
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.3
9/7/1999
Page 13 of 17
CYPRESS [ CYPRESS ]
