C9820
Direct Rambus Clock Generator
Preliminary
Transition Specifications (Cont.)
Figure 7 shows that the Clk Stop to Normal transition goes through three phases. During tCLKON, the clock output is
not specified and can have glitches. For tCLKON < t<tCLKSETL, the clock output is enabled and must be glitch-free.
For t>tCLKSETL, the clock output phase must be settled to within 50 ps of the phase before the clock output was
disabled. At this time, the clock output must also meet the voltage and timing specifications in Table 11. The outputs are
in a high impedance state during the Clk Stop mode (see Table 7). The above specification apply when the output has
been held in the ClkStop state for less than tSTOP of Table 8.
Symbol
tSTOP
tON
Min
100
Max
100
Units
µS
Description
Max time in Clk Stop (StopB=0) before re-entering Normal mode (StopB=1).
Min time in Normal mode (StopB=1) before re-entering Clk Stop (StopB=0)
nS
Table 8: StopB Control Timing
After the DRCG PLL has settled, the distributed loop containing the phase aligner must also settle. This settling time
depends on components in the distributed loop which are outside of the clock source. Therefore, this settling time is not
a component specification.
The maximum lock time for the distributed loop is specified in Table 9 below. Note that the total time for the output clock
to settle from the Powerdown state to the Normal state is the sum of tPOWERUP plus tDISTLOCK. Similarly, if the
Mult0 and Mult1 control signals are changed during the Normal state, the total time for the output clock to re-settle is the
sum of tMULT plus tDISTLOCK.
Symbol
Min
Max
5
Units
mS
Description
tDISTLOCK
Time from when Clk/ClkB output is settled to when the phase error between
SynClkN and PclkM falls with the tERR-PD spec in Table 11.
Table 9: Distributed Loop Lock Time Specification
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation,
Vin and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Ambient Temperature:
Maximum Power Supply:
-0.3V
0.3V
0ºC to + 125ºC
0ºC to +70ºC
7V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.3
9/7/1999
Page 11 of 17
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