+/+
Preliminary
PIN No.
37,38,41
44
50
53,55
46, 48, 52
CPU
CPU/2
…when timing is critical
C9817
133 MHz I
2
C Clock Generator for mobile Pentium
®
III / Rambus Systems
Pin Description (Cont.)
Pin Name
3V66 (0,2)
PWR
VDD
VDDC
VDDC/2
VDDI
I/O
O
O
O
O
TYPE
Description
3.3 V Fixed 66.6Mhz Hub-link clock outputs. Synchronous to
CPU clocks.
2.5 V Host bus clock output. Programmable per Table1,
page1.
2.5 V DRCG clock output. Half CPU frequency and
synchronous to CPU clock.
2.5 V APIC clock outputs. Fixed at 16.67MHz and
synchronous to CPU clock.
No connect
IOAPIC(0,1)
N/C
PU = Internal 250K Pull-up
Power Plane Distribution
PIN No.
5
8
11,18,19,26
Pin Name
VDDR
VDD
VDDP
Power to pins
2,3,4,6,7
10,12,13,16,17,
20,21,24,25,27,
28
30
32,33,34,35,37,
38,41
44
50
53,55
Description
3.3 V Power Supply for reference output clocks and crystal circuitry.
3.3V Analog Core Power Supply.
3.3V common power supply pin for PCI clocks and input
programming pins (Spread#, PWR_DN#, SEL133/100#)
3.3 V Power Supply for 48MHz output buffer and internal PLL
circuitry.
3.3 V Power Supply for 3V66M buffers, digital core circuitry, and
input programming pins (CPU_STP#, PCI_STP#, SEL(0:1)).
Power Supply pin for CPU output buffer. Typically connected to
2.5V
Power Supply pin for CPU/2. Typically connected to 2.5V
Power Supply pin for IOAPIC(0:1). Typically connected to 2.5V
Common Ground pins.
31
39, 40
45
49
56
1,9,14,15,29,
22, 23, 36, 42,
43,47, 51,54
VDD48
VDD3V66
VDDC
VDDC/2
VDDI
VSS
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins
their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
WWW.IMICORP.COM
Rev 1.0
11/1/1999
Page 3 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
