+/+
Preliminary
Product Features
•
•
•
•
•
•
…when timing is critical
C9817
133 MHz I
2
C Clock Generator for mobile Pentium
®
III / Rambus Systems
Supports Mobile Pentium III systems.
Designed to support high speed chipset with
Rambus
I2C programmability and power management
feature
Integrates Spread Spectrum Technology for EMI
reduction
Frequency Extension feature
One CPU clock
®
•
•
•
•
•
•
•
•
2 Synchronous IOAPIC clocks
1 CPU/2 synchronous DRCG clock.
1 Free Running PCI_F clock for Power
management timing
7 Synchronous Low Skew PCI clocks (<500pS)
3 3.3V Synchronous Fixed 66.6MHz clocks
1 48MHz USB clock.
3 REF clocks for peripheral components.
Available in 56 SSOP and TSSOP packages.
Frequency Table (in MHz)
Sel133/100#
0
1
CPU
100
133.3
CPU/2
50
66.6
3V66(0:2)
66.6
66.6
PCI(_F,0:6)
33.3
33.3
48MH
REF(0:2)
48
14.318
48
14.318
Table 1
IOAPIC(0:1)
16.67
16.67
Function
Normal mode, 100 MHz
Normal mode, 133.3 MHz
Block Diagram
XIN
34pF
300K
34pF
XOUT
1
REF1
VDDR
1
VDDR
REF0
Pin Configuration
VSS
REF0
FE0/REF1
FE1/REF2
VDDR
XIN
XOUT
VDD
VSS
SPREAD#
VDDP
PCI_F
PCI6
VSS
VSS
PCI5
PCI4
VDDP
VDDP
PCI3
PCI2
VSS
VSS
PCI1
PCI0
VDDP
PWR_DN#
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDI
IOAPIC1
VSS
IOAPIC0
n/c
VSS
CPU/2
VDDC/2
n/c
VSS
n/c
VDDC
CPU
VSS
VSS
3V66-2
VDD3V66
VDD3V66
3V66-1
3V66-0
VSS
SDATA
SCLK
PCI_STP#
CPU_STP#
VDD48
48MHz
VSS
VDDR
1
REF2
VDDI
fe0
fe1
apic
2
VDDC
cpu
Rin
SCLK
SDATA
SEL133/100#
PWR_DN#
CPU_STP#
PCI_STP#
SPREAD#
i2c-clk
i2c-data
s133/100#
PD#
CS#
PS#
sst#
VDDP
pci
PLL1
VDD48
Rin
48
PD#
PLL2
1
48MHZ
8
PCI(_F,0:6)
cpu/2
1
VDDC/2
1
CPU/2
CPU
IOAPIC(0:1)
VDD3V66
66m
3
3V66(0:2)
Fig. 1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
WWW.IMICORP.COM
Rev 1.0
11/1/1999
Page 1 of 19
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