+/+…when timing is critical
C9815C
Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems
Preliminary
133 MHz Host
100 MHz Host
66 MHz Host
Symbol
Parameter
Units
Min
Max
Min
69.8413
1.0
Max
71.0
4.0
Min
69.8413
1.0
Max
71.0
4.0
TPeriod
Tr / Tf
REF period5,6
REF rise and fall times7
REF Cycle to Cycle Jitter6
69.8413
71.0
4.0
nS
nS
pS
nS
nS
mS
%
1.0
-
TCCJ
-
1000
10.0
10.0
3
-
1000
10.0
10.0
3
1000
10.0
10.0
3
tpZL, tpZH
tpLZ, tpHZ
tstable
Output enable delay (all outputs)8
Output disable delay (all outputs)13
All clock Stabilization from power-up12
Duty Cycle for All outputs14
1.0
1.0
1.0
1.0
1.0
1.0
Tduty
45
55
45
55
45
55
Note 5: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6: All outputs loaded as per table 5, page 11. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at
1.25V for 2.5V signals (figs. 9A and 9B).
Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V
and 2.0V for 2.5V signals (see Fig.9A and Fig.9B)
Note 8: Measured from when both SEL1 and SEL0 are switched to high (enable).
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see
Figs. 9A & 9B)
Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency
output is stable and operating within the specifications
Note 13:Measured from when both SEL1 and SEL0 are switched to low (disable).
Note 14: Device designed for Typical Duty Cycle of 50%.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/5/2000
Page 13 of 18
CYPRESS [ CYPRESS ]
