+/+…when timing is critical
C9815C
Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems
Preliminary
DC Parameters (All outputs loaded per table 5 below) (VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%,
TA = 0º to +85ºC)
Characteristic
Symbol Min
Typ
Max
1.0
Units
Vdc
Vdc
Vdc
Vdc
µA
Conditions
Input Low Voltage
VIL1
VIH1
VIL2
VIH2
IIL1
-
-
-
-
-
Note 1
Input High Voltage
2.0
-
-
1.0
-
Input Low Voltage
Note 2
Input High Voltage
2.2
-66
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Input Low Current (@VIL = VSS)
Input High Current (@VIL = VDD)
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
-5
5
For internal Pull up resistors,
Note 6
IIH1
µA
IIL2
µA
For internal Pull Down resistors,
Note 6
IIH2
µA
Ioz
-
-
10
280
100
10
µA
Idd3.3V
Idd2.5V
Isdd
-
-
mA
mA
mA
pF
Sel2 = 0, Sel1 = Sel0 = 1
Sel2 = 0, Sel1 = Sel0 = 1
Sel1 = Sel0 = x, PD# = 0
-
-
-
-
Cin
-
-
5
Cout
Lpin
-
-
6
pF
-
-
34
7
nH
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Cxtal
VBIAS
Txs
32
0.3Vdd
-
38
pF
Measured from Pin to Ground. Note 5
From Stable 3.3V power supply.
Vdd/2
0.7Vdd
40
V
-
µS
Note1:
Note2:
Note3:
Note5:
Applicable to input signals: Sel(0:1), PD# (pull up), SEL2 (pull down)
Applicable to Sdata, and Sclk.
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications.
Note6:
Internal Pull up and Pull down resistors have a typical value of 50k (it may vary between 30K and 70K).
Clock Name
Max Load (in pF)
CPU(0:2), IOAPIC(0:1), REF, USB
PCI(0:6), SDRAM(0:7), DCLK, 3V66(0:2)
DOT
20
30
15
Table 5.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/5/2000
Page 11 of 18
CYPRESS [ CYPRESS ]
