APPROVED PRODUCT
C9777
Low EMI Clock Generator for 440BX, ALi1631 & Via Pro133+ / Pentium®III Systems
Pin Description
PIN No.
Pin Name
SI0
PWR I/O TYPE
Description
1
2
I
This is a bi-directional pin (see app. note, p.4). At power up, it is an
input select pin, SI0 for Selecting the frequency at pin23. When the
power reaches the rail, the data is latched into the control registers,
and this pin becomes
A buffer output of the reference signal at Xin (typically a crystal).
This is a bi-directional pin (see app. note, p.4). At power up, it is an
input select pin, SDWN# for Selecting the center or down spread
spectrum. When the power reaches the rail, the data is latched into
the control registers, and this pin becomes
VDD
O
I
REF1
SDWN#
PU
VDD
VDD
O
I
A buffer output of the reference signal at Xin (typically a crystal).
REF2
Xin
4
5
OSC1 Reference oscillator input pin. Requires either an external parallel
resonant crystal (nominally 14.318 MHz) or externally generated
reference signal
OSC1 Reference oscillator output pin. Drives an external parallel resonant
crystal. When an externally generated reference signal is used at
Xin, this pin remains unconnected.
VDD
VDD
O
O
Xout
7,8,10,11,
13,14,16,1
PCI clock outputs. They are Synchronous to the CPU clocks. See
table 1 on page 1 for frequency and PCI to CPU ratio.
PCI(_F,1:7)
7
22
23
VDD
VDD
O
O
a 48MHz USB clock output
This output clock frequency is selected by Strapping SIO on pin 1
as follows:
48M
24M / 48M
If SIO = 1, then this pin is a 48MHz USB clock
If SIO = 0, then this pin is a 24 MHz SIO clock.
25,26,27
28
I
I
I
PU
PU
PU
Input Select Lines for frequency selection. They have internal Pull-
ups. See table1, p.1.
Input Line for enabling Spread Spectrum function When asserted
Low.
These pins are for power management, and are typically controlled
by the chipset South bridge. They have internal Pull-ups, and are
active LOW. (see page 3)
S2,S1,S0
SSON#
VDD
VDD
29,30,31
PWR_dwn#
CPU_stp#
PCI_stp#
When CPU_stp# = 0, then CPU (1:4) are stopped in a low state
synchronously.
When PCI_stp# = 0, then PCI (1:7) are stopped in a low state
synchronously.
When PWR_dwn# = 0, then all clocks are stopped as well as
internal circuitry.
35,36,39,4
0
44,45
VDD
C
VDDI
O
O
O
Host (CPU) Clock outputs. See Table 1,p.1 for frequency selection.
CPU(1:4)
IOAPIC(1:2)
REF3
Buffered output clock of reference oscillator at Xin. (typically a
crystal at 14.31818MHz)
REF buffer output of the reference clock at Xin. (typically a crystal at
14.31818MHz)
47
VDD
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07048 Rev. **
05/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 2 of 12
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