C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
Crystal and Reference Oscillator Parameters
Characteristic
Frequency
Symbol
Fo
Min
Typ
Max
16.00
+/-100
+/- 100
5
Units
MHz
PPM
PPM
PPM
Conditions
12.00
14.31818
Tolerance
TC
-
-
-
-
-
-
-
Calibration Note 1
TS
Stability (Ta -10 to +60C) Note 1
Aging (first year @ 25C) Note 1
Parallel Resonant
TA
Mode
OM
CP
-
-
Pin Capacitance
32
pF
Capacitance of XIN and Xout pins to
ground (each)
DC Bias Voltage
Startup time
VBIAS
Ts
0.3Vdd
Vdd/2
0.7Vdd
V
µS
-
-
-
-
16
-
30
-
Load Capacitance
CL
pF
See calculation section below
Note 1
Effective Series
resistance (ESR)
R1
40
Ohms
Power Dissipation
Shunt Capacitance
DL
-
-
-
0.10
8
mW
pF
Crystal’s internal package
capacitance (total)
CO
--
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
Clock generator internal pin capacitance of 32 pF, Load to the crystal is therefore
The total capacitance see by the crystal would therefore be
=
=
=
2.0 pF
16.0 pF
18.0 pF.
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07014 Rev. **
5/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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