C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
AC Parameters
Characteristic
Symbol
Min
40
12
45
0
Typ
50
Max
60
Units
%
Conditions
When external reference is used
Input (REF) Duty Cycle
REF input frequency
Output Duty Cycle
-
FREF
-
14.3
50
16
MHz
%
55
Measured at 1.5V
Skew from any output to any
output
tOFFCC
200
500
pS
30 pF Load, Measured at 1.5V
(all outputs fall within a 500 pSec time
window)
Jitter Cycle to Cycle
Output Freq.
tJpp
FO
-250
30
-
+250
70
pS
MHz
pS
Any Output
33/66
At device output pins
Long term output jitter
Power up to output lock time
tJlt
-500
-
-
-
+500
10
Any output, 2 minute sample
mS
Measured from the point VDD reaches
3.15 Volts with a stable reference
T TL
R
OE Rising to Output Lock
time
TOEL
-
-
3
mS
Mesured in a stabilized environment
where OE has been previously been
brought to a logic low level.
Input Capacitance
CIN
-
-
4
pF
(FBIN and REF pins)
VDD = VDDA =3.3V ±5%, TA = 0ºC to +70ºC
Buffer Characteristics (All Output Clocks))
Characteristic
Symbol
IOHmin
IOHmax
IOLmin
IOLmax
TRmin
Min
22
Typ
Max
Units
mA
mA
mA
mA
nS
Conditions
Vout = VDD - .5V
Vout = 1.5V
Vout = 0.4V
Vout = 1.5V
30 pF Load
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
-
-
-
-
-
-
-
-
-
-45
26
65
Rise Time Min
0.4
2.5
Between 0.4 V and 2.4 V
VDD= VDDA = 3.3V ±5%, TA = 0ºC to +70ºC
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07014 Rev. **
5/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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