BCM89359 Advance Data Sheet
PCI Express Interface
8B/10B Encoder/Decoder
The PCIe core on the BCM89359 uses an 8b/10b encoder/decoder scheme to provide DC balancing,
synchronizing clock and data recovery, and error detection. The transmission code is specified in the ANSI
X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4.
Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a
6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to
encode one of the 12 special symbols included in the 8b/10b transmission code. These code groups are
concatenated to form a 10-bit symbol, which is then transmitted serially. The special symbols are used for link
management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.
Elastic FIFO
An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock
domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a
result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively
adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique
reduces the elastic FIFO size and the average receiver latency by half.
Electrical Subblock
The high-speed signals utilize the common mode logic (CML) signaling interface with on-chip termination and
deemphasis for best-in-class signal integrity. A deemphasis technique is employed to reduce the effects of
intersymbol interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case
channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to
receive data with acceptable bit-error rate (BER).
To further minimize ISI, multiple bits of the same polarity that are output in succession are deemphasized.
Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for
maximum interoperability while minimizing the complexity of controlling the deemphasis values. The high-speed
interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the receiver.
The range of AC capacitance allowed is 75 nF to 200 nF.
Configuration Space
The PCIe function in the BCM89359 implements the configuration space as defined in the PCI Express Base
Specification v3.0.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 63
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