BCM89359 Advance Data Sheet
PCM Interface
PCM Interface Timing
Short Frame Sync, Master Mode
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
BT_PCM_CLK
4
BT_PCM_SYNC
BT_PCM_OUT
8
HIGH IMPEDANCE
7
5
6
BT_PCM_IN
Table 6: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Reference Characteristics
Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
PCM bit clock frequency
–
–
–
–
–
–
–
–
–
12
–
MHz
ns
PCM bit clock LOW
PCM bit clock HIGH
BT_PCM_SYNC delay
BT_PCM_OUT delay
BT_PCM_IN setup
BT_PCM_IN hold
41
41
0
–
ns
25
25
–
ns
0
ns
8
ns
8
–
ns
Delay from rising edge of BT_PCM_CLK during
last bit period to BT_PCM_OUT becoming high
impedance.
0
25
ns
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 42
BROADCOM CONFIDENTIAL
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