BCM89359 Advance Data Sheet
List of Figures
List of Figures
Figure 1: BCM89359 Functional Block Diagram ............................................................................................... 1
Figure 2: BCM89359 Block Diagram .............................................................................................................. 15
Figure 3: Typical Power Topology (1.2V)......................................................................................................... 18
Figure 4: Typical Power Topology (2.5V and 3.3V) ......................................................................................... 19
Figure 5: Recommended Oscillator Configuration ........................................................................................... 23
Figure 6: Recommended Circuit to Use with an External Reference Clock..................................................... 24
Figure 7: Startup Signaling Sequence ............................................................................................................. 34
Figure 8: CVSD Decoder Output Waveform Without PLC............................................................................... 36
Figure 9: CVSD Decoder Output Waveform After Applying PLC..................................................................... 36
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 42
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 43
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 44
Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 45
Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)......................................................... 46
Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 47
Figure 16: USB Composite Device Configuration............................................................................................ 48
Figure 17: USB Full-Speed Timing .................................................................................................................. 49
Figure 18: UART Timing .................................................................................................................................. 51
Figure 19: I2S Transmitter Timing.................................................................................................................... 54
Figure 20: I2S Receiver Timing........................................................................................................................ 54
Figure 21: Multipoint Global Coexistence Interface ......................................................................................... 56
Figure 22: Legacy 3-Wire LTE Coexistence Interface ..................................................................................... 57
Figure 23: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 60
Figure 24: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 60
Figure 25: PCI Express Layer Model............................................................................................................... 61
Figure 26: WLAN MAC Architecture ................................................................................................................ 64
Figure 27: WLAN PHY Block Diagram............................................................................................................. 69
Figure 28: BCM89359 WLBGA Ball Map, A1–J12 (Package Bottom View — Balls Facing Up) ..................... 71
Figure 29: BCM89359 WLBGA Ball Map, K1–V12(Package Bottom View — Balls Facing Up)...................... 72
Figure 30: RF Port Location for Bluetooth Testing........................................................................................... 96
Figure 31: Port Locations (Applies to 2.4 GHz) ............................................................................................. 103
Figure 32: Port Locations (Applies to 5 GHz) ................................................................................................ 103
Figure 33: SDIO Bus Timing (Default Mode) ................................................................................................. 130
Figure 34: SDIO Bus Timing (High-Speed Mode).......................................................................................... 132
Figure 35: SDIO Clock Timing (SDR Modes) ................................................................................................ 133
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 9
BROADCOM CONFIDENTIAL
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