BCM88335 Data Sheet
Generic SPI Mode
Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 23.
Figure 23: gSPI Command Structure
BCM_SPID Command Structure
27
31 30 29 28
11 10
0
C
A
F1 F 0
Address – 17 bits
P acket length - 11bits *
*11’h0 = 2048 by tes
F unction N o: 00 – F unc Ϭ0͗ꢀꢁůůꢀ^W/ꢀƐƉĞĐŝĮĐꢀƌĞŐŝƐƚĞƌƐ
01 – F unc 1: Registers and meories belonging to other blocks in the chip (64 bytes max)
10 – F unc 2: DMA channel 1. WLAN packets up to 2048 bytes.
11 – F unc 3ϯ͗ꢀꢂDꢁꢀĐŚĂŶŶĞůꢀϮꢀ;ŽƉƟŽŶĂůͿ͘ꢀWĂĐŬĞƚƐꢀƵƉꢀƚŽꢀϮϬϰϴꢀďLJƚĞƐ͘
Acce ss : 0 – F ixed add ress
1 – Incremental add ress
C ommand : 0 – R ead
1 – Write
Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS
going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data
on the active edge.
Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the
first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to
represent the first bit of the following data word. This allows data to be ready for the first clock edge without
relying on asynchronous delays.
Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs
from the write/read command in the following respects: a) chip selects go high between the command/address
and the data and b) the time interval between the command/address is not fixed.
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 60
BROADCOM CONFIDENTIAL
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