BCM88335 Data Sheet
Sequencing of Reset and Regulator Control Signals
Figure 46: WLAN = ON, Bluetooth = OFF
32.678 kHz
Sleep Clock
90% of VH
VBAT*
VDDIO
~ 2 Sleep cycles
WL_REG_ON
100 ms
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
3. Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high. BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high.
Figure 47: WLAN = OFF, Bluetooth = ON
32.678 kHz
Sleep Clock
90% of VH
VBAT*
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 134
BROADCOM CONFIDENTIAL
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