BCM88335 Data Sheet
SDIO/gSPI Timing
Table 45: SDIO Bus Timinga Parameters (High-Speed Mode)
Symbol Minimum Typical Maximum Unit
Parameter
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
Clock high time
–
ns
Clock rise time
3
ns
Clock fall time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total system capacitance (each line)
CL
40
a. Timing is based on CL 40pF load on CMD and Data.
b. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 123
BROADCOM CONFIDENTIAL
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