BCM88335 Data Sheet
SDIO/gSPI Timing
Table 44: SDIO Bus Timinga Parameters (Default Mode) (Cont.)
Parameter
Symbol
Minimum Typical
Maximum Unit
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL 40pF load on CMD and Data.
b. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 35 and Table 45 on page 123.
Figure 35: SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 122
BROADCOM CONFIDENTIAL
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