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BCM43907KWBGT 参数 Datasheet PDF下载

BCM43907KWBGT图片预览
型号: BCM43907KWBGT
PDF下载: 下载PDF文件 查看货源
内容描述: [WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor]
分类和应用:
文件页数/大小: 128 页 / 2500 K
品牌: CYPRESS [ CYPRESS ]
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BCM43907 Preliminary Data Sheet  
Applications Subsystem  
Section 4: Applications Subsystem  
Overview  
The Applications subsystem contains the general use CPU, memory, the standalone DMA core, the  
cryptography core, and the majority of the external interfaces.  
Applications CPU and Memory Subsystem  
This subsystem has an integrated 32-bit ARM Cortex-R4 processor with an internal 32 KB D-cache and an  
internal 32 KB I-cache. The ARM Cortex-R4 is a low-power processor that features a low gate count, low  
interrupt latency, and low-cost debugging capabilities. It is intended for deeply embedded applications that  
require fast interrupt response features. The ARM Cortex-R4 implements the ARM v7-R architecture and  
supports the Thumb-2 instruction set.  
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available,  
outperforming 8- and 16-bit devices on a MIPS/µW basis. It also supports integrated sleep modes.  
Using multiple technologies to reduce cost, the ARM Cortex-R4 enables improved memory utilization, reduced  
pin overhead, and reduced silicon area. It also has extensive debugging features, including real-time tracing of  
program execution.  
On-chip memory for the CPU includes 1 MB SRAM, 640 KB ROM, and an 8 KB RAM powered independently  
of the application subsystem.  
Memory-to-Memory DMA Core  
The BCM43907 memory-to-memory DMA (M2MDMA) engine contains eight DMA channel pairs, each  
containing one transmit/pull engine and one receive/push engine.  
The DMA engine provides general purpose data movement between memories that can be on the device,  
attached directly to the device, or accessed through a host interface. The transmit/pull engine reads data from  
the source memory and immediately passes it to the paired receive/push engine, which proceeds to write it to  
the destination memory. Multiple masters can program the individual channels, and multiple interrupts are  
provided so that interrupts for different channels can be routed separately to different masters.  
Broadcom®  
March 12, 2016 • 43907-DS104-R  
Page 28  
BROADCOM CONFIDENTIAL  
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