BCM43907 Preliminary Data Sheet
JTAG and ARM Serial Wire Debug
Table 5 shows the MCLK rates (in MHz) associated with each of the various sample rates. In the table, FS refers
to the sample rate in kHz and typical MCLK rates are shaded.
Table 5: Variable Sample Rate and MCLK Rate Supporta
MCLK Rate (MHz)b
Sample
Rate (kHz) 128 × FS 192 × FS 256 × FS 384 × FS 512 × FS 640 × FS 768 × FS 1152 × FS
8
1.024
1.536
2.048
2.8224
3.072
4.096
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
–
3.072
4.096
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
32.768
–
5.12
7.056
7.68
10.24
14.112
15.36
20.48
28.224
30.72
–
6.144
8.4672
9.216
12.288
16.9344
18.432
24.576
33.8688
36.864
–
9.216
11.025
12
1.4112
1.536
2.1168
2.304
4.2336
4.608
12.7008
13.824
16
2.048
3.072
6.144
18.432
22.05
24
2.8224
3.072
4.2336
4.608
8.4672
9.216
25.4016
27.648
32
4.096
6.144
12.288
16.9344
18.432
24.576
33.8688
36.864
–
36.864
44.1
48
5.6448
6.144
8.4672
9.216
–
–
–
–
–
–
64
8.192
12.288
16.9344
18.432
36.864
88.2
96
11.2896
12.288
24.576
–
–
–
–
–
192
–
–
–
a. All data in the table assumes a crystal frequency of 37.4 MHz.
b. MCLK frequency errors are less than 1 ppb.
For an MCLK specification, see Table 44 on page 104.
An external MCLK source can be provided to the device instead of using the internal MCLK source.
2
The BCM43907 needs an external clock source input on the slave clock pin for the I S interface to work properly
2
in Slave mode. The slave clock frequency is dependent upon the audio sample rate and the external I S codec.
JTAG and ARM Serial Wire Debug
The BCM43907 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and
PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist
customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is
highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.
The BCM43907 also supports ARM Serial Wire Debug (SWD) for connecting a JTAG debugger directly to both
ARM Cortex-R4s. For SWD, the combination of a clock and a bidirectional signal (on a single pin) provides
normal JTAG debug and test functionality. The reduced pin-count SWD interface is a high-performance
alternative to the JTAG interface.
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 32
BROADCOM CONFIDENTIAL
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