BCM4354 Data Sheet
Pinout and Signal Descriptions
Section 13: Pinout and Signal Descriptions
Ball Maps
Figure 33 and Figure 34 on page 85 show the WLBGA ball map.
Figure 33: WLBGA Ball Map, 4.87 mm × 7.67 mm Array, 192-Ball, A1–V6 (Bottom View—Balls Facing Up)
6
5
4
3
2
1
HSIC_DATA
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_TDN
PCIE_TDP
A
B
C
D
E
PCIE_PLL
_AVDD1P2
PCIE_RXTX
_AVDD1P2
HSIC_AGND12PLL
HSIC_DVDD12
VSSC
PCIE_PLL_AVSS
PCIE_PME_L
PCIE_RXTX_AVSS
PCIE_PERST_L
VDDC
PCIE_RDN
PCIE_RDP
PCIE_TESTP
VSSC
PCIE_TESTN
PCIE_CLKREQ_L
BT_USB_DN
GPIO_9
BT_VDDC
FM_AUDIOVDD1P2
FM_AOUT1
FM_AOUT2
LPO_IN
BT_USB_DP
CLK_REQ
FM_PLLVDD1P2
FM_PLLVSS
F
FM_AUDIOVSS
FM_VCOVSS
BT_I2S_DO
BT_I2S_DI
VSSC
FM_LNAVCOVDD1P2
FM_RFIN
G
H
J
BT_UART_RXD
BT_UART_TXD
BT_UART_RTS_L
BT_UART_CTS_L
BT_VDDC
BT_PCM_OUT
BT_PCM_IN
BT_GPIO_4
BT_DEV_WAKE
VSSC
BT_VDDC
FM_LNAVSS
BT_VCOVSS
BT_PLLVDD1P2
BT_PAVSS
BT_I2S_CLK
BT_PCM_SYNC
BT_I2S_WS
BT_HOST_WAKE
BT_IFVDD1P2
BT_PLLVSS
BT_VCOVDD1P2
BT_LNAVDD1P2
BT_RF
K
L
BT_PCM_CLK
BT_IFVSS
BT_PAVDD2P5
M
N
P
R
T
WRF_RX2G
_GND1P2_CORE0
WRF_LNA_2G
_GND1P2_CORE0
WRF_RFIN
_2G_CORE0
RF_SW_CTRL_4
RF_SW_CTRL_6
WRF_AFE
_GND1P2_CORE0
WRF_TX
_GND1P2_CORE0
WRF_PA2G_VBAT
_GND3P3_CORE0
WRF_RFOUT
_2G_CORE0
WRF_LOGEN
_GND1P2
WRF_LOGENG
_GND1P2
WRF_GPIO
_OUT_CORE0
WRF_PADRV_VBAT
_VDD3P3_CORE0
WRF_PA2G_VBAT
_GND3P3_CORE0
WRF_PA2G_VBAT
_VDD3P3_CORE0
WRF_MMD
_GND1P2
WRF_MMD
_VDD1P2
WRF_PFD
_VDD1P2
WRF_PADRV_VBAT
_GND3P3_CORE0
WRF_PA5G_VBAT
_GND3P3_CORE0
WRF_PA5G_VBAT
_VDD3P3_CORE0
WRF_BUCK
_VDD1P5
CORE0
WRF_VCO
_GND1P2
WRF_PFD
_GND1P2
WRF_TSSI_A
_CORE0
WRF_PA5G_VBAT
_GND3P3_CORE0
WRF_RFOUT
_5G_CORE0
U
V
WRF_SYNTH
_VBAT_VDD3P3
WRF_CP
_GND1P2
WRF_BUCK
_GND1P5_CORE0
WRF_RX5G
_GND1P2_CORE0
WRF_LNA_5G
_GND1P2_CORE0
WRF_RFIN
_5G_CORE0
6
5
4
3
2
1
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 84
BROADCOM CONFIDENTIAL
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