BCM4354 Data Sheet
PCI Express Interface
Figure 28 shows the blocks in the HSIC device core.
Key features of HSIC include:
•
•
•
•
•
High-speed 480 Mbps data rate
Source-synchronous serial interface using 1.2V LVCMOS signal levels
No power consumed except when a data transfer is in progress
Maximum trace length of 10 cm.
No Plug-n-Play support, no hot attach/removal
Figure 28: HSIC Device Block Diagram
32-Bit On-Chip Communication System
DMA Engines
F I O s F T X
F I F T O X
s O F I F T X
F I O s F T X
F I F T O X
s
s
RX FIFO
TX FIFOs
Endpoint Management Unit
USB 2.0 Protocol Engine
HSIC PHY
Strobe
Data
PCI Express Interface
The PCI Express (PCIe™) core on the BCM4354 is a high-performance serial I/O interconnect that is protocol
compliant and electrically compatible with the PCI Express Base Specification v3.0 running at Gen1 speeds.
This core contains all the necessary blocks, including logical and electrical functional subblocks to perform PCIe
functionality and maintain high-speed links, using existing PCI system configuration software implementations
without modification.
Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as
shown in Figure 29. A configuration or link management block is provided for enumerating the PCIe
configuration space and supporting generation and reception of System Management Messages by
communicating with PCIe layers.
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 71
BROADCOM CONFIDENTIAL
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