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BCM4354XKUBGT 参数 Datasheet PDF下载

BCM4354XKUBGT图片预览
型号: BCM4354XKUBGT
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver]
分类和应用:
文件页数/大小: 192 页 / 4575 K
品牌: CYPRESS [ CYPRESS ]
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BCM4354 Data Sheet  
UART Interface  
UART Interface  
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins. Refer to  
Table 26: “GPIO Alternative Signal Functions,” on page 120. Provided primarily for debugging during  
development, this UART enables the BCM4354 to operate as RS-232 data termination equipment (DTE) for  
exchanging and managing data with other serial devices. It is compatible with the industry standard 16550  
UART, and provides a FIFO size of 64 × 8 in each direction.  
JTAG Interface  
The BCM4354 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and  
PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist  
customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is  
highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.  
Refer to Table 26: “GPIO Alternative Signal Functions,” on page 120 for JTAG pin assignments.  
SPROM Interface  
Various hardware configuration parameters may be stored in an external SPROM instead of the OTP. The  
SPROM is read by system software after device reset. In addition, depending on the board design, customer-  
specific parameters may be stored in SPROM.  
The four SPROM control signals —SPROM_CS, SPROM_CLK, SPROM_MI, and SPROM_MO are  
multiplexed on the SDIO interface (see Table 26: “GPIO Alternative Signal Functions,” on page 120 for  
additional details). By default, the SPROM interface supports 2 kbit serial SPROMs, and it can also support  
4 kbit and 16 kbit serial SPROMs by using the appropriate strapping option.  
SFLASH Interface  
For use only when the HSIC interface mode is selected, an interface to external SFLASH is available.  
The four SFLASH control signals —SFLASH_CS#, SFLASH_CLK, SFLASH_MI, and SFLASH_MO are  
multiplexed on the SDIO interface (see Table 26: “GPIO Alternative Signal Functions,” on page 120 for  
additional details).  
Broadcom®  
October 15, 2014 • 4354-DS109-R  
Page 68  
BROADCOM CONFIDENTIAL  
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