BCM43455 Preliminary Data Sheet
Pin Descriptions
Table 19: Signal Descriptions (Cont.)
Signal Name
WLBGA Ball
D7
Type
Description
PCI_PME_L
OD
PCI power management event output.
Used to request a change in the device
or system power state. The assertion
and deassertion of this signal is
asynchronous to the PCIe reference
clock. This signal has an open-drain
output structure, as per the PCI Bus
Local Bus Specification, Revision 2.3.
WLAN SDIO Bus Interface
Note: These signals can also have alternate functionality depending on package and host interface mode.
SDIO_CLK
A7
C6
C7
B7
B6
A6
I
SDIO clock input.
SDIO command line.
SDIO data line 0.
SDIO data line 1.
SDIO data line 2.
SDIO data line 3.
SDIO_CMD
I/O
I/O
I/O
I/O
I/O
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
WLAN GPIO Interface
Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific
functions.
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_13
GPIO_14
GPIO_15
GPIO_16
C1
D3
D4
D2
E4
E3
D1
E1
G5
F4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Programmable GPIO pins:
GPIO_2 is TCK/SWCLK if
JTAG_SEL = 1
GPIO_3 is TMS/SWDIO if
JTAG_SEL = 1
GPIO_4 is TDIO if JTAG_SEL = 1
GPIO_5 is TDO if JTAG_SEL = 1
GPIO_6 is TRST_L if JTAG_SEL = 1
F3
D11
D10
K7
K6
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 86
BROADCOM CONFIDENTIAL
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