BCM43455 Preliminary Data Sheet
Pin Descriptions
Pin Descriptions
The signal name, type, and description of each pin in the BCM43455 is listed in Table 19. The symbols shown
under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down
characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
Table 19: Signal Descriptions
Signal Name
WLBGA Ball
Type
Description
WLAN and Bluetooth Receive RF Signal Interface
WRF_RFIN_2G
N8
I
2.4 GHz Bluetooth and WLAN receiver
shared input.
WRF_RFIN_5G
L11
N9
I
5 GHz WLAN receiver input.
2.4 GHz WLAN PA output.
5 GHz WLAN PA output.
WRF_PAOUT_2G
WRF_PAOUT_5G
WRF_EXT_TSSIA
O
O
I
M11
K8
5 GHz TSSI input from an optional
external power amplifier/power detector.
WRF_GPAIO_OUT
L8
I/O
GPIO or 2.4 GHz TSSI input from an
optional external power amplifier/power
detector.
RF Switch Control Lines
RF_SW_CTRL_0
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_3
RF_SW_CTRL_4
RF_SW_CTRL_5
RF_SW_CTRL_6
RF_SW_CTRL_7
RF_SW_CTRL_8
F11
F10
G9
G8
F7
O
O
O
O
O
O
O
O
O
Programmable RF switch control lines.
The control lines are programmable via
the driver and NVRAM file.
G7
G6
F6
E6
WLAN PCI Express Interface
PCIE_CLKREQ_L
B8
OD
PCIe clock request signal which
indicates when the REFCLK to the PCIe
interface can be gated.
1 = the clock can be gated.
0 = the clock is required.
PERST_L
D8
I (PU) PCIe System Reset. This input is the
PCIe reset as defined in the PCIe Base
Specification Version 1.1.
PCIE_RDN
A9
I
Receiver differential pair (×1 lane).
PCIE_RDP
A8
I
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_TDN
C11
B11
A10
B10
I
PCIe differential clock inputs (negative
and positive), 100 MHz differential.
I
O
O
Transmitter differential pair (×1 lane).
PCIE_TDP
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 85
BROADCOM CONFIDENTIAL
CYPRESS [ CYPRESS ]
