CYW4343X
Figure 4. CYW4343X Block Diagram
Cortex
M3
Debug
AHB
FM RX
FM RF
FM Digital
AHB to APB
FM
ADC
ADC
Bridge
RAM
ROM
FM Demod.
MDX RDS
Decode
I/F
LNA
APB
FM_RX
Patch
InterCtrl
DMA
WD Timer
SW Timer
Control
LO
Gen.
RSSI
DPLL
Bus Arb
ARM IP
GPIO
Ctrl
JTAG supported over SDIO or BT PCM
SDIO or gSPI
SWREG
LDOx2
LPO
XTAL OSC.
POR
Power
Supply
Sleep CLK
XTAL
BPL
UART
PMU
Control
Buffer
SDIO
gSPI
Modem
RF
PA
Digital
Demod.
& Bit
APU
WL_REG_ON
Debug
UART
BT Clock/
Hopper
Sync
ARM
CM3
WDT
OTP
Digital
I/O
BlueRF
Interface
Digital
Mod.
PCM
GPIO
UART
JTAG*
GPIO
UART
LCU
RAM
Supported over SDIO or BT PCM
RX/TX
Buffer
ROM
GPIO
IF
PLL
BT PHY
BT‐WLAN
ECI
Wake/
WiMax Coex
Sleep Ctrl
BTFM Clock Control
Clock
2.4 GHz
PA
Sleep‐
time
Keeping
PMU
Ctrl
PMU
Management
Shared LNA
BPF
WiMax
Coex.
XO
Buffer
LPO
POR
WLAN
PTU
* Via GPIO configuration, JTAG is supported over SDIO or BT PCM
Document No. 002-14797 Rev. *H
Page 8 of 128
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