CYW4343X
1. Overview
1.1 Overview
The Cypress CYW4343X provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor
solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343X is
designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 3 on page 7 Figure 4 on page 8 Figure 3 on page 7 shows the interconnection of all the major physical blocks in the CYW4343X and their associated external inter-
faces, which are described in greater detail in subsequent sections.
Figure 3. CYW4343X Block Diagram
C ortex
D ebug
M 3
AH B
FM RX
FM RF
FM D igital
AH B to APB
Bridge
A D C
A D C
FM
I/F
RAM
RO M
FM D em od.
M D X RDS
D ecode
LN A
APB
FM _RX
Patch
InterCtrl
D M A
W D Tim er
SW Tim er
Control
LO
G en.
RSSI
D PLL
Bus Arb
ARM IP
G PIO
Ctrl
JTAG supported over SD IO or BT PC M
SD IO or gSPI
SW REG
LD O x2
LPO
XTAL O SC.
PO R
Pow er
Supply
Sleep C LK
XTAL
BPL
U ART
PM U
Control
Buffer
SD IO
gSPI
M odem
D igital
D em od.
RF
PA
APU
W L_REG _O N
D ebug
U ART
BT C lock/
H opper
&
Bit
Sync
ARM
C M 3
W DT
O TP
D igital
I/O
BlueRF
Interface
I2S/PC M
D igital
M od.
G PIO
U ART
JTAG *
G PIO
U ART
LCU
RAM
Supported over SDIO or BT PCM
RX/TX
Buffer
RO M
G PIO
IF
PLL
BT PH Y
BT‐W LAN
ECI
W ake/
BTFM Clock Control
C lock
Co ex
2.4 G Hz
PA
SWleiMepax Ctrl
Sleep‐
tim e
Keeping
PM U
Ctrl
PM U
M anagem ent
Shared LN A
BPF
W iM ax
Coex.
XO
Buffer
LPO
PO R
W LAN
PTU
* Via G PIO configuration , JTAG is supported over SDIO or BT PCM
Document No. 002-14797 Rev. *H
Page 7 of 128
CYPRESS [ CYPRESS ]
