CYW4343X
Figure 8. Typical Power Topology (2 of 2)(4343S)
CYW4343S_WPT
1.8V, 2.5V, and 3.3V
6.4 mA
WL BBPLL/DFLL
WL OTP 3.3V
LDO3P3 with
Back‐Power
VOUT_3P3
WLRF_PA_VDD
480 to 800 mA
6.4 mA
VBAT
Protection
WL RF—PA (2.4 GHz)
LDO_
VDDBAT5V
1 uF
0201
4.7 uF
0402
(Peak 450‐800 mA
200 mA Average) 3.3V
2.5V Cap‐less
LNLDO
WL RF—ADC, AFE, LOGEN,
LNA, NMOS Mini‐PMU LDOs
22
ohm
(10 mA)
SW2
Peak: 92 mA
Average: 75 mA
Resistance: 1 ohm
Placed inside WL Radio
WPT_3P3
Peak: 70 mA
Average: 15 mA
BT_PAVDD
BT Class 1 PA
1 uF
0201
Power switch
No power switch
External to chip
Supply ball
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document No. 002-14797 Rev. *H
Page 15 of 128
CYPRESS [ CYPRESS ]
