CYW4343X
Figure 7. Typical Power Topology (1 of 2)
SR_VDDBAT5V
WL RF—TX Mixer and PA
(not all versions)
VBAT
Mini PMU
CYW4343X
1.2V
Internal VCOLDO
1.2V
1.2V
1.2V
WL RF—LOGEN
WL RF—RX LNA
WL RF—ADC REF
WL RF—TX
80 mA (NMOS)
Internal RXLDO
10 mA (NMOS)
VBAT:
Operational:
Performance:
2.4—4.8V
3.0—4.8V
VDD1P35
Internal ADCLDO
10 mA (NMOS)
Absolute Maximum: 5.5V
VDDIO
Operational:
Internal TXLDO
80 mA (PMOS)
1.2V
1.2V
1.8—3.3V
1.35V
Internal AFELDO
80 mA (NMOS)
WL RF—AFE and TIA
Core Buck
Regulator
10 mA average,
> 10 mA at start‐up
WL RF—RFPLL PFD and MMD
SR_VLX
Mini PMU is placed
in WL radio
Int_SR_VBAT
Peak: 370 mA
WLRF_XTAL_
VDD1P2
Avg: 170 mA
2.2 uH
(320 mA)
SW1
600 @
100 MHz
0603
WL RF—XTAL
1.2V
LDO_VDD_1P5
LNLDO
SR_VBAT5V
FM_RF_VDD
4.6 mA
6.4 mA
(100 mA)
VBAT
GND
FM LNA, Mixer, TIA, VCO
4.7 uF
0402
VOUT_LNLDO
0.1 uF
0201
SR_PVSS
2.2 uF
0402
BTFM_PLL_VDD
BT_VCO_VDD
PMU_VSS
FM PLL, LOGEN, Audio DAC/BT PLL
BT LNA, Mixer, VCO
BT_IF_VDD
BT ADC, Filter
WCC_VDDIO
WCC_VDDIO
LPLDO1
(5 mA)
1.1V
(40 mA)
WLAN/BT/CLB/Top, Always On
WL OTP
VDDC1
VDDC2
1.3V, 1.2V,
or 0.95V
(AVS)
CL LDO
Peak: 200 mA
Avg: 80 mA
(Bypass in deep‐
sleep)
2.2 uF
0402
VOUT_CLDO
WL Digital and PHY
WL_REG_ON
BT_REG_ON
o_wl_resetb
o_bt_resetb
WL VDDM (SROMs & AOS)
Power switch
No power switch
Supply ball
Ground ball
Supply bump/pad
Ground bump/pad
External to chip
BT VDDM
BT Digital
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
BT/WLAN reset
balls
Document No. 002-14797 Rev. *H
Page 14 of 128
CYPRESS [ CYPRESS ]
