Ball Maps
BCM4339 Preliminary Data Sheet
Figure 39: 145-Ball WLBGA (Top View)
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10
11
12
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
A
B
C
A
SR_PVSS
SR_VLX
WL_REG_ON
LPO_IN
GPIO_6
GPIO_3
GPIO_0
GPIO_1
HSIC_DATA
HSIC_STROBE
RREFHSIC
SDIO_DATA_0
SDIO_DATA_1
SDIO_CLK
SDIO_CMD
WL_VDDC
B
C
SR_VDDBATP5V
LDO_VDD1P5
SR_VDDBATA5V PMU_AVSS
GPIO_4
WL_VDDC
HSIC_AVDD12PLL
HSIC_DVDD12
VDDIO_SD
SDIO_DATA_3
VOUT_CLDO
BT_REG_ON
VSSC
GPIO_7
GPIO_5
GPIO_2
VSSC
HSIC_AGNDPLL
SDIO_DATA_2
RF_SW_CTRL_8
VSSC
RF_SW_CTRL_4
D
E
F
D
E
F
VOUT_3P3
VOUT_LNLDO
JTAG_SEL
BT_UART_CTS VDDIO_RF
VSSC
RF_SW_CTRL_3
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_0
VOUT_BTLDO2P5
LDO_VDDBAT5V VDDIO
RF_SW_CTRL_9 BT_UART_RTS BT_UART_TXD
RF_SW_CTRL_5
BT_PCM_IN
GPIO_8
BT_PCM_CLK
WL_VDDC
BT_VDDIO
BT_VDDC
WL_VDDC
BT_VDDC
VSSC
BT_UART_RXD RF_SW_CTRL_7
WL_VDDC
BBPLL_AVS
WRF_XTAL_GND1P2
WRF_XTAL_VDD1P5
WRF_CP_GND
BBPLL_AVDD1P2
WRF_XTAL_IN
G
H
J
G
H
J
BT_PCM_SYNC CLK_REQ
BT_I2S_WS
BT_I2S_CLK
WRF_GPIO_OUT
WRF_TSSI_A
WRF_WL_LNLDOIN_VDD1P5 RF_SW_CTRL_6
WRF_VCO_GND
WRF_PFD_GND1P2
FM_AUDIOVDD1P2 BT_HOST_WAKE BT_PCM_OUT
WRF_BUCK_GND1P5
WRF_MMD_GND1P2
WRF_XTAL_OUT
FM_AOUT1
FM_AOUT2
FM_VCOVSS
FM_AUDIOVSS BT_DEV_WAKE VSSC
FM_PLLVDD1P2 FM_PLLVSS BT_IFVDD1P2
FM_LNAVSS BT_VCOVSS
BT_VCOVDD1P2 BT_LNAVDD1P2 BT_RF
BT_I2S_DI
BT_I2S_DO
BT_IFVSS
WRF_AFE_GND1P2
WRF_RX2G_GND1P2
WRF_LO_GND1P2_2
WRF_TX_GND1P2
WRF_SYNTH_VBAT_VDD3P3 WRF_MMD_VDD1P2
WRF_PFD_VDD1P2
WRF_XTAL_VDD1P2
WRF_RX5G_GND1P2
K
L
K
L
BT_PLLVSS
WRF_PADRV_VBAT_VDD3P3 WRF_PADRV_VBAT_GND3P3 WRF_LO_GND1P2_2
BT_PLLVDD1P2 BT_PAVSS
BT_AGPIO
WRF_LNA_2G_GND1P2 WRF_PA_VBAT_GND3P3_4 WRF_PA_VBAT_GND3P3_3 WRF_PA_VBAT_GND3P3_2 WRF_PA_VBAT_GND3P3_1 WRF_LNA_5G_GND1P2
M
N
M
N
FM_LNAVCOVDD1P2 FM_RFIN
BT_PAVDD2P5 WRF_RFIN_2G
WRF_RFOUT_2G
8
WRF_PA2G_VBAT_VDD3P3 WRF_PA5G_VBAT_VDD3P3 WRF_RFOUT_5G
WRF_RFIN_5G
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Broadcom®
November 17, 2014 • 4339-DS106-R
Page 95
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